-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library altera;
use altera.altera_syn_attributes.all;

entity testboard is
	port (
		CLOCK_50 : in std_logic;
		LCD_EN : out std_logic;
		LCD_RS : out std_logic;
		LCD_RW : out std_logic;
		LCD_DATA : inout std_logic_vector(7 downto 0);
		LCD_ON : inout std_logic;
		LCD_BLON : inout std_logic;
		ENET_CLK : out std_logic;
		ENET_CMD : out std_logic;
		ENET_CS_N : out std_logic;
		ENET_DATA : inout std_logic_vector(15 downto 0);
		ENET_INT : in std_logic;
		ENET_RD_N : out std_logic;
		ENET_RST_N : out std_logic;
		ENET_WR_N : out std_logic;
		SW : in std_logic_vector(15 downto 0);
		KEY : in std_logic_vector (0 downto 0); --reset pushbutton
		LEDR : out std_logic_vector(17 downto 0);
		LEDG : out std_logic_vector(8 downto 0);
		GPIO_0 : inout std_logic_vector(35 downto 0);
		GPIO_1 : inout std_logic_vector(35 downto 0)
	);

end testboard;

architecture structure of testboard is

signal RX_DATA : std_logic_vector(3 downto 0);
signal RX_CLK : std_logic;
signal RX_DV : std_logic;
signal TX_DATA : std_logic_vector(3 downto 0);
signal TX_CLK : std_logic;
signal TX_DV : std_logic;
signal MII_CLK : std_logic;

component mii_phy is
	port (
		SWITCHES : in std_logic_vector(15 downto 0);
		LED_RED : out std_logic_vector(17 downto 0);
		LED_GREEN : out std_logic_vector(8 downto 0);
		IO : inout std_logic_vector(35 downto 0);
		EXT_CLK : in std_logic;
		--GPIO_1 : in std_logic_vector(0 to 35);
		RX_DATA : out std_logic_vector(3 downto 0);
		RX_CLK : inout std_logic;
		RX_DV : out std_logic;
		TX_DATA : out std_logic_vector(3 downto 0);
		TX_CLK : inout std_logic;
		TX_DV : out std_logic
	);
end component mii_phy;

component nios_system is 
	port (
		-- 1) global signals:
		signal clk : IN STD_LOGIC;
		signal rcv_clk : IN STD_LOGIC;
		signal reset_n : IN STD_LOGIC;
		signal xmt_clk : IN STD_LOGIC;
		
		-- the_dm9000a_0
		signal ENET_CLK_from_the_dm9000a_0 : OUT STD_LOGIC;
		signal ENET_CMD_from_the_dm9000a_0 : OUT STD_LOGIC;
		signal ENET_CS_N_from_the_dm9000a_0 : OUT STD_LOGIC;
		signal ENET_DATA_to_and_from_the_dm9000a_0 : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		signal ENET_INT_to_the_dm9000a_0 : IN STD_LOGIC;
		signal ENET_RD_N_from_the_dm9000a_0 : OUT STD_LOGIC;
		signal ENET_RST_N_from_the_dm9000a_0 : OUT STD_LOGIC;
		signal ENET_WR_N_from_the_dm9000a_0 : OUT STD_LOGIC;
		signal iOSC_50_to_the_dm9000a_0 : IN STD_LOGIC;

		-- the_lcd_16207_0
		signal LCD_E_from_the_lcd_16207_0 : OUT STD_LOGIC;
		signal LCD_RS_from_the_lcd_16207_0 : OUT STD_LOGIC;
		signal LCD_RW_from_the_lcd_16207_0 : OUT STD_LOGIC;
		signal LCD_data_to_and_from_the_lcd_16207_0 : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);

		-- the_rcv_data
		signal in_port_to_the_rcv_data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

		-- the_rcv_dv
		signal in_port_to_the_rcv_dv : IN STD_LOGIC;

		-- the_xmt_data
		signal out_port_from_the_xmt_data : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

		-- the_xmt_dv
		signal out_port_from_the_xmt_dv : OUT STD_LOGIC
	);
end component nios_system;

begin
--LEDG(8 downto 0) <= "101010101";
--GPIO_0(34) <= CLOCK_50;
--GPIO_0(35) <= MII_CLK;
-- Create 25MHz MII_CLK
process (CLOCK_50)
begin
	if (CLOCK_50'EVENT and CLOCK_50 = '1') then
		MII_CLK <= not MII_CLK;
	end if;
end process;

-- Instantiate an MII PHY
MII: mii_phy port map (
	SWITCHES => SW,
	LED_RED => LEDR,
	LED_GREEN => LEDG,
	IO => GPIO_0,
	EXT_CLK => MII_CLK,
	RX_DATA => RX_DATA,
	RX_CLK => RX_CLK,
	RX_DV => RX_DV,
	TX_DATA => TX_DATA,
	TX_CLK => TX_CLK,
	TX_DV => TX_DV
);

-- Instantiate the Nios II system entity generated by the SOPC Builder
NiosII: nios_system port map (
	clk => CLOCK_50,
	rcv_clk => RX_CLK,
	reset_n => KEY(0),
	xmt_clk => TX_CLK,
	ENET_CLK_from_the_dm9000a_0 => ENET_CLK,
	ENET_CMD_from_the_dm9000a_0 => ENET_CMD,
	ENET_CS_N_from_the_dm9000a_0 => ENET_CS_N,
	ENET_DATA_to_and_from_the_dm9000a_0 => ENET_DATA(15 downto 0),
	ENET_INT_to_the_dm9000a_0 => ENET_INT,
	ENET_RD_N_from_the_dm9000a_0 => ENET_RD_N,
	ENET_RST_N_from_the_dm9000a_0 => ENET_RST_N,
	ENET_WR_N_from_the_dm9000a_0 => ENET_WR_N,
	iOSC_50_to_the_dm9000a_0 => CLOCK_50,
	LCD_E_from_the_lcd_16207_0 => LCD_EN,
	LCD_RS_from_the_lcd_16207_0 => LCD_RS,
	LCD_RW_from_the_lcd_16207_0 => LCD_RW,
	LCD_data_to_and_from_the_lcd_16207_0 => LCD_DATA(7 downto 0),
	in_port_to_the_rcv_data => RX_DATA,
	in_port_to_the_rcv_dv => RX_DV,
	out_port_from_the_xmt_data => TX_DATA,
	out_port_from_the_xmt_dv => TX_DV
);
end structure;